This invention relates to a control interface system for use with a memory device executing variable length instructions, such as a speech synthesis device, and more specifically to such a control interface system in which the circuits included therein are implementable in integratable field effect semiconductor devices.
Interface circuits which connect a control device, typically a microprocessor, to a memory device, are known in the prior art. It is typical for the control device to be kept executing "wait" states until the memory device has executed the instruction. An example of this solution may be found on pages 4-15 through 4-18 of Texas Instrument's 9900 Family Systems Design (1st Edition).
Disclosed herein is a speech synthesizer which is preferably controlled by the central processing unit of a home-type computer. It will, of course, be appreciated by those skilled in the art, that any interface between a memory device and a control device wherein the memory device cannot properly respond within the minimum access time determined by the system clock, may incorporate the interface system of this invention. Additionally, it is preferable that the interface between the speech synthesizer and the central processing unit be more efficient that those solutions known in the prior art.
It was, therefore, one object of this invention that the circuits included in a control interface system for use with memory devices be implemented in integratable field effect semiconductor devices.
It was another object of this invention to provide an improved control interface system for controlling a memory device with a control device.
It was yet another object of this invention to provide an improved control interface system for implementing variable length instructions with a control device.
It was yet another object of this invention to provide an improved control interface system for use with a speech synthesis device and a central processing unit, wherein the execution time of which the speech synthesis device is capable is relatively slow as compared to that of the central processing unit.
The foregoing objects are achieved as is now described. A control latch is utilized to release the control device after an instruction has been initiated. A plurality of latches, each set by the conclusion of the execution of a previous instruction, are utilized to reset the control latch. An attempted access of the memory device during the execution of a previous command will result in suspending the operation of the control device until such time as the previous instruction is concluded and the new instruction is initiated.